Recently, A/D converters have been used for various electronic devices, and improvement of the conversion speed and accuracy has been demanded.
FIG. 1 is a block diagram illustrating an example of a conventional A/D converter that is a 3-bit parallel A/D converter.
As illustrated in FIG. 1, the A/D converter includes a control signal generation circuit 101, an encoder 102, a reference voltage generation circuit 103, and a plurality of comparators C1 to C7.
The control signal generation circuit 101 receives a reference clock CLK and generates a comparator control signal CNT1 for comparators C1 to C7 and an encoder control signal CNT2 for the encoder 102.
The A/D converter is an N bit (3-bit) parallel A/D converter that converts output signals O1 to O7 of the number of 2N−1 (seven) comparators C1 to C7 into thermometer codes, and outputs the digital signals (binary codes) converted by the encoder 102.
The reference voltage generation circuit 103 includes eight resistances R that are serially coupled between a high potential reference voltage VRH and a low potential reference voltage VRL, and a reference voltage for respective comparators C1 to C7 is taken out from a node that couples two adjacent resistances. Note that among eight resistances R, resistances of both ends to which reference voltages VRH and VRL are directly applied are set, for example, to a half of the other resistances.
FIG. 2 illustrates an operation of a comparator of the A/D converter illustrated in FIG. 1.
As illustrated in FIG. 2, a comparator control signal CNT1 from the control signal generation circuit 101 in the A/D converter illustrated in FIG. 1 has substantially the same duty ratio (duty) as the reference clock CLK that is 50% (0.5). The duty ratio is defined as a ratio of a time in one cycle in which a pulse is at a high level H.
Thus, the comparators C1 to C7 perform sampling for a period of a half of one cycle, and perform comparison for the remaining half period.
Relative variations (for example, manufacturing variations) exist among the number of 2N−1 (seven) comparators C1 to C7 in the above described A/D converter. Hence, the sampling and comparison accuracies differ depending on comparators.
The longer the processing times (sampling time and comparison time) are, the more accurate the sampling processing and comparison processing becomes. Insufficient sampling time and comparison time cause bubbles in thermometer codes due to relative variations among comparators C1 to C7, and thereby characteristics of the A/D converter may be degraded.
FIG. 3 illustrates generation of bubbles in the A/D converter illustrated in FIG. 1. The left half of the figure illustrates a case in which no bubble is generated, while the right half illustrates a case where a bubble is generated at the output O5 of the comparator C5.
In other words, the thermometer codes O1 to O7 output from the comparators C1 to C7 become “1110000” when no bubble is generated and the 3-bit digital signal D0 to D2 is correctly output as “110.”
On the other hand, when a bubble is generated at the thermometer code O5 output from the comparators C1 to C7, the thermometer codes O1 to O7 become “1110100” and the encoder 102 does not output digital signals D0 to D2.
A related technique is known that ignores a thermometer code in which a bubble is generated, in other words, assumes the thermometer code as 0 and outputs digital signals D0 to D2.
As described above, an A/D converter with an encoder provides a function to correct a bubble error in an input thermometer code. This encoder includes an encode unit that generates a digital signal of a Gray code by detecting a logic border of a thermometer code and a Gray-binary conversion unit that converts a Gray code output from the encode unit into a digital signal of a binary code.
The encode unit includes an error detection unit that detects whether or not two values of bits of Gray codes have a specific relation, and thereby detects an error code included in the Gray codes. Furthermore, the encode unit includes an error correction unit that corrects error codes detected by the error detection unit.
Moreover, an A/D converter is proposed that controls a duty ratio of a sampling clock depending on conditions.
The proposed A/D converter includes a sample hold circuit, an A/D converter circuit, an A/D output determination circuit, and a sample clock generation circuit. An analog input signal is input to the sample-hold circuit. The sample-hold circuit operates based on a sample clock. The A/D conversion circuit generates a digital output signal from an output of the sample-hold circuit.
The A/D output determination circuit outputs a duty control signal based on the digital output signal. The sample clock generation circuit adjusts a duty ratio of the sampling clock based on the duty control signal and supplies the sample clock to the sample-hold circuit.
As described above, there are A/D converters that generate bubble errors due to relative variations among comparators in which sampling and comparison accuracies differ depending on comparators.
Moreover, an A/D converter is known that ignores a thermometer code in which a bubble is generated and outputs binary codes, however such A/D converter causes reduction of conversion accuracy.